Texas A&M University-Kingsville

Laboratory Assignments

Laboratory Handouts

Course Schedule

Lecture Lab. Assignment Important Dates,  Assignments
Jan. 22 VHDL Language Concepts, Simulation, Synthesis    Hw 1.3-1.7
Jan.. 29 Structure, Behavior Modeling
 Hw 2.1-2.7
Feb. 5 Sequential Statements, Delay Modeling VHDL Hierarchical  Design  Hw 3.1-3.7
Feb. 12 Hazards, Process, Wait Statement Hazards Free Design  Hazard Problem
Feb. 19 Attributes, Generate, Exam Review Test Benches Hw 9.1 9.4
Feb. 26 Generic, Hardware Testing Test Benches 2
 Exam1: Feb. 24
Mar. 5 Arithmetic Operations ALU Design 
 64-bit Adder Problem
Mar. 12 Subprograms, Overloading ALU Synthesis  Hw 6.1-6.9
Mar. 19 Spring Break  --   --
Mar. 26 Packages, Libraries and Configuration ALU Synthesis_2  Hw 7.1-7.7, 10.1-10.5
Apr. 2 State Machines State Machine Design  FSM Realization
Apr. 9 Design with SM Charts State Machine Design 2
Exam2: Apr. 7
Apr. 16 Programmable Logic Technology FSM-VHDL State CAD
Apr. 23 Logic Synthesis FSM-VHDL State CAD 2
 State Reduction
Apr. 30 Asynchronous Sequential Design System Synthesis  FSM Design and Simulation
May 7 Final exam review System Synthesis 2  Testing
May 11   Lab Notebook Due at Final  Exam3

Teaching Assistant contact & Schedule

Shreyas Basavaraju

E-mail: shreys.b@gmail.com      Lab Schedule (EEEN 4355-100):

Wednesday 2:00 - 4:30

Shilpa Kaila

E-mail:  shilpareddy13@gmail.com          Lab Schedule (EEEN 4355-101):

Thursday 2:00 - 4:30

    This page was last updated on: November 18, 2012