Topics covered:
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Introduction to VHDL
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Introduction to EDA tools
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Variables ,Signals, and Constants
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Entity and architectures
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Operators
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Flow control
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Attributes
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Functions and procedures
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Packages and libraries
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Arrays
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File I/O
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Generics
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Generate statements
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Hazards
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VHDL test benches
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Networks for arithmetic operations
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Serial adder
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Parallel ripple adder/subtracter
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Carry select and carry look ahead
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Multiplier and divider
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Register design
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Programmable logic devices
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PLA
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PAL
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CPLD
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FPGA
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Synthesis and design procedure for CPLD and FPGA devices
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VHDL Synthesis
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State machine
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SM chart
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ROM realization
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PAL realization
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VHDL and state encoding techniques
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Reduction of state tables
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Equivalent states
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Equivalent sequential networks
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Asynchronous Networks
Click here for Course schedule & Lab Resources
This page was last updated on: November 18, 2012