Texas A&M University-Kingsville

EEEN 4310


Course Schedule:

  • Lec 1  
    • Overview of VLSI design issues
 READING LIST
Chapter 1
 HOMEWORK LIST
  • Lec 2
    • Electrical properties of MOS transistors
    • Depletion and enhancement mode
    • Threshold voltage
    • Simple MOSFET fabrication steps (MOSFET Fabrication)
 Sections: 3.1, 3.3
 
  • Lec 3
    • Transistor operation (MOSFET Operation)
    • Regions of operation
    • Trans. Char. equations, current equations
    • Body effect
 Section 3.4
3.7
3.11
  • Lec 4
    • Pinch off region
    • Channel length modulation 
    • Gate capacitance, diffusion capacitance, routing capacitance
 Sections 3.4, 3.6
3.16
  • Lec 5  
    • Inverter Characteristics
    • Gain ratio
    • Noise margin
 Sections 5.1, 5.4
5.1
5.4a

  • Lec 6
    • Switching Characteristic
      • Fall time
      • Rise time
 Sections 6.1, 6.2
5.6
5.9a
  • Lec 7
    • Delays
      • Propagation delay
      • Empirical delay  model
      • Gate delay approximation
      • Body effect and delay
    • Latch up
 Sections 6.3, 6.4, 13.6
Gate Delay
  • Lec 8
    • CMOS process technology 
      • Crystal growth, wafer fabrication
 Chapter 2, Training videos
Exam 1:  lectures 1-7  
  • Lec 9
    • CMOS process enhancements
      • Wafer testing, packaging, mutichip technology
 Chapter 2, Training videos  CMOS Fabrication Report
  • Lec 10
    • Thin film deposition
    • Photolithography
 Chapter 2, Training videos  Inverter Characteristic (Hspice)
  • Lec 11
    • Etching process
    • Ion Implantation
 Chapter 2, Training videos  CMOS Fabrication Report
  • Lec 12
    • Delay Analysis for basic gates
 Sections 7.1, 7.2
Delay and Ring Oscillator (Hspice)
 Sections 7.3, 7.4
 Design in class assigned gates
  • Lec 14
    • Modeling with SPICE
 Chapter 4, Handouts
Exam 2:  lectures 8-13
  • Lec 15
    • VLSI CAD tools
    • Layout Design, DRC
 Handouts, Software Manual
 
  • Lec 16
    • Technology file set up 
    • Scalable layout design
    • Tapeout and file formats
 Handouts, Software Manual
  • Lec 17
    • Performance estimation
    • Transistor sizing
 Section 7.4
Gate Design (HSpice)

 Size in class assigned networks
  • Lec 18
    • CMOS power dissipation
    • Transmission gates
 Sections 6.7, 7.5, 11.2


11.5
  • Lec 19
    • Wire model
    • Alternative design techniques (Pseudo nmos, CVSL,  etc.)
 Sections 6.5, 6.6
Self Loading(Hspice)
  • Lec 20 
    • Chip input/output circuits 
    • Pad and power connections 
 Sections 13.1, 13.2, 13.3
Performance and sizing problems

13.3
  • Lec 21-22
    • Alternative CMOS gates (Dynamic gates, etc.)
 Chapter 9
 9.3
 9.7a
 9.8
  • Lec 23
    • BiCMOS gate design
 Chapter 12
 12.6
  • Lec 24-26
    • Design of memory and other programmable devices
 Chapter 10
 Final Exam

This page was last updated on: November 18, 2012